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1-/2-/4-channel digital potentiometers ad8400/ad8402/ad8403 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. features 256-position variable resistance device replaces 1, 2, or 4 potentiometers 1 k? , 10 k ? , 50 k ? , 100 k ? power shutdownless than 5 a 3-wire,spi-compatible serial data input 10 mhz update data loading rate 2.7 v to 5.5 v single-supply operation qualified for automotive applications applications mechanical potentiometer replacement programmable filters, delays, time constants volume control, panning line impedance matching power supply adjustment general description the ad8400/ad8402/ad8403 provide a single-, dual-, or quad-channel, 256-position, digitally controlled variable resistor (vr) device. 1 these devices perform the same electronic adjust- ment function as a mechanical potentiometer or variable resistor. the ad8400 contains a single variable resistor in the compact soic-8 package. the ad8402 contains two independent variable resistors in space-saving soic-14 surface-mount packages. the ad8403 contains four independent variable resistors in 24-lead pdip, soic, and tssop packages. each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by the digital code loaded into the controlling serial input register. the resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the vr latch. each variable resistor offers a completely programmable value of resistance between the a terminal and the wiper or the b terminal and the wiper. the fixed a-to-b terminal resistance of 1 k, 10 k, 50 k, or 100 k has a 1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/c. a unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs, avoiding any make-before-break or break-before-make operation. (continued on page 3) 1 the terms digital potentiometer, vr, and rdac are used interchangeably. functional block diagram 8 8-bit latch ck rs 8 8-bit latch ck rs 8 8-bit latch ck rs 8 8-bit latch ck rs dac select a1, a0 1 10-bit serial latch ck rs q d sdo shdn rs ad8403 v dd dgnd sdi clk cs 8 2 3 2 4 rdac1 w1 a1 b1 agnd1 rdac2 w2 a2 b2 agnd2 rdac3 w3 a3 b3 agnd3 rdac4 w4 a4 b4 agnd4 shdn shdn shdn shdn 0 1092-001 figure 1. code (decimal) 100 75 50 25 0 0 64 128 192 255 r wa (d), r wb (d) (% of nominal r ab ) r wa r wb 01092-002 figure 2. r wa and r wb vs. code
ad8400/ad8402/ad8403 rev. e | page 2 of 32 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 4 ? electrical characteristics10 k version ................................ 4 ? electrical characteristics50 k and 100 k versions ......... 6 ? electrical characteristics1 k version .................................. 8 ? electrical characteristicsall versions ................................. 10 ? timing diagrams ........................................................................ 10 ? absolute maximum ratings .......................................................... 11 ? serial data-word format .......................................................... 11 ? esd caution................................................................................ 11 ? pin configurations and function descriptions ......................... 12 ? typical performance characteristics ........................................... 14 ? test circuits ..................................................................................... 19 ? theory of operation ...................................................................... 20 ? programming the variable resistor ......................................... 20 ? programming the potentiometer divider ............................... 21 ? digital interfacing ...................................................................... 21 ? applications ..................................................................................... 24 ? active filter ................................................................................. 24 ? outline dimensions ....................................................................... 26 ? ordering guide .......................................................................... 30 ? automotive products ................................................................. 31 ? revision history 7/10rev. d to rev. e changes to features section ............................................................ 1 changes to i ab continuous current parameter (table 5) ......... 11 updated outline dimensions ........................................................ 26 changes to ordering guide ........................................................... 30 added automotive products section ........................................... 31 10/05rev. c to rev. d updated format .................................................................. universal changes to features ........................................................................... 1 changes to table 1 ............................................................................. 4 changes to table 2 ............................................................................. 6 changes to table 3 ............................................................................. 8 changes to table 5 ........................................................................... 11 added figure 36 ............................................................................... 18 replaced figure 37 .......................................................................... 19 changes to theory of operation section ..................................... 20 changes to applications section ................................................... 24 updated outline dimensions ........................................................ 26 changes to ordering guide ........................................................... 28 11/01rev. b to rev. c addition of new figure ..................................................................... 1 edits to specifications ....................................................................... 2 edits to absolute maximum ratings .............................................. 6 edits to tpcs 1, 8, 12, 16, 20, 24, 35 ............................................... 9 edits to the pro gramming the variable resistor section .......................... 13
ad8400/ad8402/ad8403 rev. e | page 3 of 32 general description (continued from page 1) each vr has its own vr latch that holds its programmed resistance value. these vr latches are updated from an spi- compatible, serial-to-parallel shift register that is loaded from a standard 3-wire, serial-input digital interface. ten data bits make up the data-word clocked into the serial input register. the data-word is decoded where the first two bits determine the address of the vr latch to be loaded, and the last eight bits are the data. a serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple vr applications without additional external decoding logic. the reset ( rs ) pin forces the wiper to midscale by loading 80 h into the vr latch. the shdn pin forces the resistor to an end- to-end open-circuit condition on the a terminal and shorts the wiper to the b terminal, achieving a microwatt power shutdown state. when shdn is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. the digital interface is still active in shutdown so that code changes can be made that will produce new wiper positions when the device is taken out of shutdown. the ad8400 is available in the soic-8 surface mount. the ad8402 is available in both surface-mount (soic-14) and 14-lead pdip packages, while the ad8403 is available in a narrow-body, 24-lead pdip and a 24-lead, surface-mount package. the ad8402/ad8403 are also offered in the 1.1 mm thin tssop-14/tssop-24 packages for pcmcia applications. all parts are guaranteed to operate over the extended industrial temperature range of ?40c to +125c.
ad8400/ad8402/ad8403 rev. e | page 4 of 32 specifications electrical characteristics10 k version v dd = 3 v 10% or 5 v 10%, v a = v dd , v b = 0 v, ?40c t a +125c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode (specifications apply to all vrs) resistor differential nl 2 r-dnl r wb , v a = no connect ?1 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = no connect ?2 1/2 +2 lsb nominal resistance 3 r ab t a = 25c, model: ad840xyy10 8 10 12 k resistance tempco r ab /t v ab = v dd , wiper = no connect 500 ppm/c wiper resistance r w v dd = 5v, i w = v dd /r ab 50 100 r w v dd = 3v, i w = v dd /r ab 200 nominal resistance match r/r ab ch 1 to ch 2, ch 3, or ch 4, v ab = v dd , t a = 25c 0.2 1 % dc characteristics potentiometer divider (specifications apply to all vrs) resolution n 8 bits integral nonlinearity 4 inl ?2 1/2 +2 lsb differential nonlinearity 4 dnl v dd = 5 v ?1 1/4 +1 lsb dnl v dd = 3 v, t a = 25c ?1 1/4 +1 lsb dnl v dd = 3 v, t a = ?40c to +85c ?1.5 1/2 +1.5 lsb voltage divider tempco v w /t code = 80 h 15 ppm/c full-scale error v wfse code = ff h ?4 ?2.8 0 lsb zero-scale error v wzse code = 00 h 0 1.3 2 lsb resistor terminals voltage range 5 v a, b, w 0 v dd v capacitance 6 ax, capacitance bx c a, b f = 1 mhz, measured to gnd, code = 80 h 75 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h 120 pf shutdown current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.01 5 a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = 5 v 100 200 digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v output logic high v oh r l = 2.2 k to v dd v dd ? 0.1 v output logic low v ol i ol = 1.6 ma, v dd = 5 v 0.4 v input current i il v in = 0 v or 5 v, v dd = 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 a supply current (ttl) 8 i dd v ih = 2.4 v or 0.8 v, v dd = 5.5 v 0.9 4 ma power dissipation (cmos) 9 p diss v ih = v dd or v il = 0 v, v dd = 5.5 v 27.5 w power supply sensitivity pss v dd = 5 v 10% 0.0002 0.001 %/% pss v dd = 3 v 10% 0.006 0.03 %/%
ad8400/ad8402/ad8403 rev. e | page 5 of 32 parameter symbol conditions min typ 1 max unit dynamic characteristics 6 , 10 bandwidth ?3 db bw_10 k r = 10 k 600 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.003 % v w settling time t s v a = v dd , v b = 0 v, 1% error band 2 s resistor noise voltage e nwb r wb = 5 k, f = 1 khz, rs = 0 9 nv/hz crosstalk 11 c t v a = v dd , v b = 0 v ?65 db 1 typical represents average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see the test circuit in figure 38. i w = 50 a for v dd = 3 v and i w = 400 a for v dd = 5 v for the 10 k versions. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditio ns. see the test circuit in figure 37. 5 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on t he measured terminal. the remaining resistor terminals are left open circuit. 7 measured at the ax terminals. all ax terminals are open-circuited in shutdown mode. 8 worst-case supply current is consum ed when the input logic level is at 2.4 v, a st andard characteristic of cmos logic. see fig ure 28 for a plot of i dd vs. logic voltage. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = 5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change.
ad8400/ad8402/ad8403 rev. e | page 6 of 32 electrical characteristics50 k and 100 k versions v dd = 3 v 10% or 5 v 10%, v a = v dd , v b = 0 v, ?40c t a +125c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode (specifications apply to all vrs) resistor differential nl 2 r-dnl r wb , v a = no connect ?1 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = no connect ?2 1/2 +2 lsb nominal resistance 3 r ab t a = 25c, model: ad840xyy50 35 50 65 k r ab t a = 25c, model: ad840xyy100 70 100 130 k resistance tempco r ab /t v ab = v dd , wiper = no connect 500 ppm/c wiper resistance r w v dd = 5v, i w = v dd /r ab 50 100 r w v dd = 3v, i w = v dd /r ab 200 nominal resistance match r/r ab ch 1 to ch 2, ch 3, or ch 4, v ab = v dd , t a = 25c 0.2 1 % dc characteristics potentiometer divider (specifications apply to all vrs) resolution n 8 bits integral nonlinearity 4 inl ?4 1 +4 lsb differential nonlinearity 4 dnl v dd = 5 v ?1 1/4 +1 lsb dnl v dd = 3 v, t a = 25c ?1 1/4 +1 lsb dnl v dd = 3 v, t a = ?40c to +85c ?1.5 1/2 +1.5 lsb voltage divider tempco v w /t code = 80 h 15 ppm/c full-scale error v wfse code = ff h ?1 ?0.25 0 lsb zero-scale error v wzse code = 00 h 0 +0.1 +1 lsb resistor terminals voltage range 5 v a , v b , v w 0 v dd v capacitance 6 ax, bx c a , c b f = 1 mhz, measured to gnd, code = 80 h 15 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h 80 pf shutdown current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.01 5 a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = 5 v 100 200 digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v output logic high v oh r l = 2.2 k to v dd v dd ? 0.1 v output logic low v ol i ol = 1.6 ma, v dd = 5 v 0.4 v input current i il v in = 0 v or 5 v, v dd = 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 a supply current (ttl) 8 i dd v ih = 2.4 v or 0.8 v, v dd = 5.5 v 0.9 4 ma power dissipation (cmos) 9 p diss v ih = v dd or v il = 0 v, v dd = 5.5 v 27.5 w power supply sensitivity pss v dd = 5 v 10% 0.0002 0.001 %/% pss v dd = 3 v 10% 0.006 0.03 %/%
ad8400/ad8402/ad8403 rev. e | page 7 of 32 parameter symbol conditions min typ 1 max unit dynamic characteristics 6 , 10 bandwidth ?3 db bw_50 k r = 50 k 125 khz bw_100 k r = 100 k 71 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.003 % v w settling time t s _50 k v a = v dd , v b = 0 v, 1% error band 9 s t s _100 k v a = v dd , v b = 0 v, 1% error band 18 s resistor noise voltage e nwb _50 k r wb = 25 k, f = 1 khz, rs = 0 20 nv/hz e nwb _100 k r wb = 50 k, f = 1 khz, rs = 0 29 nv/hz crosstalk 11 c t v a = v dd , v b = 0 v ?65 db 1 typicals represent averag e readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see the test circuit in figure 38. i w = v dd /r for v dd = 3 v or 5 v for the 50 k and 100 k versions. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at vw with the rdac configured as a po tentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditio ns. see the test circuit in figure 37. 5 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on t he measured terminal. the remaining resistor terminals are left open circuit. 7 measured at the ax terminals. all ax terminals are open-circuited in shutdown mode. 8 worst-case supply current consumed when input logic level at 2.4 v, standard characteristic of cm os logic. see figure 28 for a plot of i dd vs. logic voltage. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = 5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change.
ad8400/ad8402/ad8403 rev. e | page 8 of 32 electrical characteristics1 k version v dd = 3 v 10% or 5 v 10%, v a = v dd , v b = 0 v, ?40c t a +125c, unless otherwise noted. table 3. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode (specifications apply to all vrs) resistor differential nl 2 r-dnl r wb , v a = no connect ?5 ?1 +3 lsb resistor nonlinearity 2 r-inl r wb , v a = no connect ?4 1.5 +4 lsb nominal resistance 3 r ab t a = 25c, model: ad840xyy1 0.8 1.2 1.6 k resistance tempco r ab /t v ab = v dd , wiper = no connect 700 ppm/c wiper resistance r w v dd = 5v, i w = v dd /r ab 53 100 r w v dd = 3v, i w = v dd /r ab 200 nominal resistance match r/r ab ch 1 to ch 2, v ab = v dd , t a = 25c 0.75 2 % dc characteristics potentiometer divider (specifications apply to all vrs) resolution n 8 bits integral nonlinearity 4 inl ?6 2 +6 lsb differential nonlinearity 4 dnl v dd = 5 v ?4 ?1.5 +2 lsb dnl v dd = 3 v, t a = 25c ?5 ?2 +5 lsb voltage divider temperature coefficient v w /t code = 80h 25 ppm/c full-scale error v wfse code = ff h ?20 ?12 0 lsb zero-scale error v wzse code = 00 h 0 6 10 lsb resistor terminals voltage range 5 v a , v b , v w 0 v dd v capacitance 6 ax, bx c a , c b f = 1 mhz, measured to gnd, code = 80 h 75 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h 120 pf shutdown supply current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.01 5 a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = 5 v 50 100 digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v output logic high v oh r l = 2.2 k to v dd v dd ? 0.1 v output logic low v ol i ol = 1.6 ma, v dd = 5 v 0.4 v input current i il v in = 0 v or 5 v, v dd = 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 a supply current (ttl) 8 i dd v ih = 2.4 v or 0.8 v, v dd = 5.5 v 0.9 4 ma power dissipation (cmos) 9 p diss v ih = v dd or v il = 0 v, v dd = 5.5 v 27.5 w power supply sensitivity pss v dd = 5 v 10% 0.0035 0.008 %/% pss v dd = 3 v 10% 0.05 0.13 %/%
ad8400/ad8402/ad8403 rev. e | page 9 of 32 parameter symbol conditions min typ 1 max unit dynamic characteristics 6 , 10 bandwidth ?3 db bw_1 k r = 1 k 5,000 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.015 % v w settling time t s v a = v dd , v b = 0 v, 1% error band 0.5 s resistor noise voltage e nwb r wb = 500 , f = 1 khz, rs = 0 3 nv/hz crosstalk 11 c t v a = v dd , v b = 0 v ?65 db 1 typicals represent averag e readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the rela tive step change from ideal be tween successive tap positions. see the test circuit in figure 38. i w = 500 a for v dd = 3 v and i w = 2.5 ma for v dd = 5 v for 1 k version. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at vw with the rdac configured as a po tentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditio ns. see the test circuit in figure 37. 5 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on t he measured terminal. the remaining resistor termina ls are left open circuit. 7 measured at the ax terminals. all ax terminals are open-circuited in shutdown mode. 8 worst-case supply current is consum ed when the input logic level is at 2.4 v, a st andard characteristic of cmos logic. see fig ure 28 for a plot of i dd vs. logic voltage. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = 5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change.
ad8400/ad8402/ad8403 rev. e | page 10 of 32 electrical characteristicsall versions v dd = 3 v 10% or 5 v 10%, v a = v dd , v b = 0 v, ?40c t a +125c, unless otherwise noted. table 4. parameter symbol conditions min typ 1 max unit switching characteristics 2 , 3 input clock pulse width t ch , t cl clock level high or low 10 ns data setup time t ds 5 ns data hold time t dh 5 ns clk to sdo propagation delay 4 t pd r l = 1 k to 5 v, c l 20 pf 1 25 ns cs setup time t css 10 ns cs high pulse width t csw 10 ns reset pulse width t rs 50 ns clk fall to cs rise hold time t csh 0 ns cs rise to clock rise setup t cs1 10 ns 1 typicals represent averag e readings at 25c and v dd = 5 v. 2 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on t he measured terminal. the remaining resistor termina ls are left open circuit. 3 see the timing diagram in figure 3 for location of measured values. all inpu t control voltages are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. swit ching characteristics are measured using v dd = 3 v or 5 v. to avoid false clocking, a minimum input logic slew rate of 1 v/s should be maintained. 4 propagation delay depends on the value of v dd , r l , and c l (see the applic ations section). timing diagrams dac register load a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 0 1 0 v dd 0v sdi clk v out cs 01092-003 figure 3. timing diagram 1% error band 1% t csh t css t dh ax or dx ax or dx t pd_min t pd_max a'x or d'x a'x or d'x 1 0 1 0 1 0 v dd 0v sdi (data in) clk cs v out 1 0 sdo (data out) t ds t ch t cs1 t cl t s t csw 01092-004 figure 4. detailed timing diagram 1% 1% error band 1 0 v dd v dd /2 v out t rs t s rs 01092-005 figure 5. reset timing diagram
ad8400/ad8402/ad8403 rev. e | page 11 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v, +8 v v a , v b , v w to gnd 0 v, v dd maximum current i wb , i wa pulsed 20 ma i wb continuous (r wb 1 k, a open) 1 5 ma i wa continuous (r wa 1 k, b open) 1 5 ma i ab continuous (r ab = 1 k/10 k/ 50 k/100 k) 1 2.1 ma/2.1 ma/ 540 a/540 a digital input and output voltage to gnd 0 v, 7 v operating temperature range ?40c to +125c maximum junction temperature (t j maximum) 150c storage temperature ?65c to +150c lead temperature (soldering, 10 sec) 300c package power dissipation (t j max ? t a )/ ja thermal resistance ( ja ) soic (r-8) 158c/w pdip (n-14) 83c/w pdip (n-24) 63c/w soic (r-14) 120c/w soic (r-24) 70c/w tssop-14 (ru-14) 180c/w tssop-24 (ru-24) 143c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. serial data-word format table 6. addr data b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb 2 9 2 8 2 7 2 0 1 maximum terminal current is bounde d by the maximum applied voltage across any two of the a, b, and w term inals at a given resi stance, the maximum current handling of the sw itches, and the maximum powe r dissipation of the package; vdd = 5 v. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8400/ad8402/ad8403 rev. e | page 12 of 32 pin configurations and function descriptions b1 1 gnd 2 cs 3 sdi 4 a1 8 w1 7 v dd 6 clk 5 ad8400 top view (not to scale) 01092-006 figure 6. ad8400 pin configuration 1 2 3 4 5 6 7 ad8402 b2 a2 w2 cs shdn dgnd a gnd 14 13 12 11 10 9 8 a1 w1 v dd sdi clk rs b1 top view (not to scale) 01092-007 figure 7. ad8402 pin configuration a gnd2 1 b2 2 a2 3 w2 4 b1 24 a1 23 w1 22 agnd1 21 a gnd4 5 b4 6 a4 7 b3 20 a3 19 w3 18 w4 8 agnd3 17 dgnd 9 v dd 16 shdn 10 rs 15 cs 11 clk 14 sdi 12 sdo 13 ad8403 top view (not to scale) 01092-008 figure 8. ad8403 pin configuration table 7. ad8400 pin function descriptions pin no. mnemonic description 1 b1 terminal b rdac. 2 gnd ground. 3 cs chip select input, active low. when cs returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target dac register. 4 sdi serial data input. 5 clk serial clock input, positive edge triggered. 6 v dd positive power supply. specified for operation at both 3 v and 5 v. 7 w1 wiper rdac, addr = 00 2 . 8 a1 terminal a rdac. table 8. ad8402 pin function descriptions pin no. mnemonic description 1 agnd analog ground. 1 2 b2 terminal b rdac 2. 3 a2 terminal a rdac 2. 4 w2 wiper rdac 2, addr = 01 2 . 5 dgnd digital ground. 1 6 shdn terminal a open circuit. shutdown controls variable resistor 1 and variable resistor 2. 7 cs chip select input, active low. when cs returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target dac register. 8 sdi serial data input. 9 clk serial clock input, positive edge triggered. 10 rs active low reset to midscale. sets rdac registers to 80 h . 11 v dd positive power supply. specified for operation at both 3 v and 5 v 12 w1 wiper rdac 1, addr = 00 2 . 13 a1 terminal a rdac 1. 14 b1 terminal b rdac 1. 1 all agnd pins must be connected to dgnd.
ad8400/ad8402/ad8403 rev. e | page 13 of 32 table 9. ad8403 pin function descriptions pin no. mnemonic description 1 agnd2 analog ground 2. 1 2 b2 terminal b rdac 2. 3 a2 terminal a rdac 2. 4 w2 wiper rdac 2, addr = 01 2 . 5 agnd4 analog ground 4. 1 6 b4 terminal b rdac 4. 7 a4 terminal a rdac 4. 8 w4 wiper rdac 4, addr = 11 2 . 9 dgnd digital ground. 1 10 shdn active low input. terminal a open circuit. shutdown cont rols variable resistor 1 through variable resistor 4. 11 cs chip select input, active low. when cs returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target dac register. 12 sdi serial data input. 13 sdo serial data output. open drain tr ansistor requires a pull-up resistor. 14 clk serial clock input, positive edge triggered. 15 rs active low reset to midscale. sets rdac registers to 80 h . 16 v dd positive power supply. specified for operation at both 3 v and 5 v. 17 agnd3 analog ground 3. 1 18 w3 wiper rdac 3, addr = 10 2 . 19 a3 terminal a rdac 3. 20 b3 terminal b rdac 3. 21 agnd1 analog ground 1. 1 22 w1 wiper rdac 1, addr = 00 2 . 23 a1 terminal a rdac 1. 24 b1 terminal b rdac 1. 1 all agnd pins must be connected to dgnd.
ad8400/ad8402/ad8403 rev. e | page 14 of 32 typical performance characteristics code (decimal) 10 8 0 0 32 256 64 96 128 160 192 224 6 4 2 resistance (k ) r wb r wa v dd =3v or5v r ab = 10k 01092-009 figure 9. wiper to end terminal resistance vs. code i wb current (ma) v wb voltage (v) 5 4 0 3 2 1 80 h 40 h 20 h ff h code = 10 h 05 h 012 34 567 t a =25 c v dd =5v 01092-010 figure 10. resistance linearity vs. conduction current digital input code (decimal) r-inl error (lsb) 1.0 0.5 ?1.0 0 32 256 64 96 128 160 192 224 0 ?0.5 v dd =5v t a =?40 c t a =+25 c t a =+85 c 01092-011 figure 11. resistance step position nonlinearity error vs. code wiper resistance ( ) frequen c y 60 48 0 40.0 42.5 65.0 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 36 24 12 ss = 1205 units v dd =4.5v t a =25 c 01092-012 figure 12. 10 k wiper-contact-resistance histogram digital input code (decimal) inl nonlinearity error (lsb) 1.0 0.5 ?1.0 0 32 256 64 96 128 160 192 224 0 ?0.5 t a = ?40 c t a =+25 c t a =+85 c v dd =5v 01092-013 figure 13. potentiometer divider nonlinearity error vs. code wiper resistance ( ) frequen c y 60 48 0 35 37 55 39 41 43 45 47 49 51 53 36 24 12 ss = 184 units v dd =4.5v t a =25 c 01092-014 figure 14. 50 k wiper-contact-resistance histogram
ad8400/ad8402/ad8403 rev. e | page 15 of 32 wiper resistance ( ) frequency 60 48 0 40.0 42.5 65.0 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 36 24 12 ss = 184 units v dd =4.5v t a =25 c 01092-015 figure 15. 100 k wiper-contact-resistance histogram temperature ( c) nomin a l resistance (k ) 10 8 0 ?75 ?50 125 ?25 0 25 50 75 100 6 4 2 r ab (end-to-end) r wb (wiper-to-end) code = 80 h r ab =10k 0 1092-016 figure 16. nominal resistance vs. temperature code (decimal) potentiometer mode tempco (ppm/ c) 70 60 ?10 0 32 160 64 96 128 30 20 10 0 50 40 192 224 256 v dd =5v t a =?40 c/+85 c v a =2v v b =0v 01092-017 figure 17. v wb /t potentiometer mode tempco code (decimal) rheostat mode tempco (ppm/ c) 700 600 ?100 0 32 160 64 96 128 300 200 100 0 500 400 192 224 256 v dd =5v t a = ?40 c/+85 c v a = no connect r wb measured 01092-018 figure 18. r wb /t rheostat mode tempco 500ns 5v 20mv r w (20mv/div) cs (5v/div) time 500ns/div 01092-019 figure 19. one position step change at half-scale (code 7f h to 80 h ) frequency (hz) gain (db) 6 0 ?54 10 1m 100 1k 10k 100k ?6 ?12 ?48 ?18 ?24 ?30 ?36 ?42 code = ff 80 40 20 10 08 04 02 01 t a =25 c 01092-020 figure 20. 10 k gain vs. frequency vs. code (see figure 43 )
ad8400/ad8402/ad8403 rev. e | page 16 of 32 hours of operation at 150 c r wb resistance (%) 0.75 0.50 ?0.75 0 600 100 300 400 0.25 ?0.25 ?0.50 200 500 0 average + 2 sigma average average ? 2 sigma code = 80 h v dd =5v ss = 158 units 01092-021 figure 21. long-term drif t accelerated by burn-in 5 s 5v 2v output input time 500 s/div 01092-022 figure 22. large signal settling time frequency (hz) gain (db) 0 ?6 ?48 1k 10k 1m ?30 ?36 ?42 ?12 ?24 ?18 ?54 100k 6 code = ff h 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h 01092-023 figure 23. 50 k gain vs. frequency vs. code frequency (hz) thd + noise (%) 10 0.001 10 100k 100 1k 10k 1 0.1 0.01 filter = 22khz v dd =5v t a =25 c 01092-024 figure 24. total harmonic distortion plus noise vs. frequency (see figure 41 and figure 42 ) v out (50mv/div) time 200ns/div 200ns 50mv 45.25 s 01092-025 figure 25. digital feedthrough vs. time frequency (hz) gain (db) 0 ?6 ?48 1k 10k 1m ?30 ?36 ?42 ?12 ?24 ?18 ?54 100k code = ff h 6 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h 01092-026 figure 26. 100 k gain vs. frequency vs. code
ad8400/ad8402/ad8403 rev. e | page 17 of 32 frequency (hz) x normalized gain flatness (0.1db/div) 10 10k 1m 100k 100 1k r=10k r = 100k r=50k code = 80 h v dd =5v t a =25 c 01092-027 figure 27. normalized ga in flatness vs. frequency (see figure 43 ) digital input voltage (v) i dd ? supply current (ma) 10 1 0.01 0.1 t a =25 c v dd =5v v dd =3v 01234 01092-028 5 figure 28. supply current vs. digital input voltage frequency (hz) psrr (db) 80 0 100 1m 1k 10k 100k 60 40 20 v dd =+5vdc 1v p-p ac t a =25 c code = 80 h c l = 10pf v a =4v,v b =0v 01092-029 figure 29. power supply reje ction ratio vs. frequency (see figure 40 ) frequency (hz) gain (db) 0 ?6 1k 10k 1m ?30 ?36 ?42 ?12 ?24 ?18 100k 6 12 v in = 100mv rms v dd =5v r l =1m f ?3db = 700khz, r = 10k f ?3db = 71khz, r = 100k f ?3db = 125khz, r = 50k 01092-030 figure 30. ?3 db bandwidths frequency (hz) i dd ? supply current ( a) 1k 1m 10m 10k 100k 1200 1000 800 600 400 200 0 a b c d a: v dd =5.5v code = 55 h b: v dd =3.3v code = 55 h c: v dd =5.5v code = ff h d: v dd =3.3v code = ff h 01092-031 t a =25 c figure 31. supply current vs. clock frequency v bias (v) r on ( ) 160 0 140 80 60 40 20 120 100 0123456 t a =25 c v dd =2.7v v dd =5.5v 01092-032 figure 32. ad8403 incremental wiper on resistance vs. v dd (see figure 39 )
ad8400/ad8402/ad8403 rev. e | page 18 of 32 frequency (hz) phase (degrees) 100k 2m 200k 1m 0 ?10 ?20 0 ?45 ?90 400k 4m 6m 10m gain (db) v dd =5v t a =25 c wiper set at half-scale 80 h 01092-033 figure 33. 1 k gain and phase vs. frequency temperature ( c) i a shutdown current (na) 100 1 ?55 ?35 10 v dd =5v ?15 5 25 45 65 85 105 125 01092-034 figure 34. shutdown current vs. temperature temperature ( c) i dd ? supply current ( a) 1 0.1 0.001 ?55 ?35 ?15 5 25 45 65 85 105 125 0.01 v dd =5.5v v dd =3.3v logic input voltage = 0, v dd 01092-035 figure 35. supply current vs. temperature code (decimal) 01092-057 0 3 2 1 4 5 6 0 32 64 96 128 160 192 224 256 theoretical i wb_max (ma) r ab = 1k v a = v b = open t a =25 c r ab = 10k r ab = 50k r ab = 100k figure 36. i wb_max vs. code
ad8400/ad8402/ad8403 rev. e | page 19 of 32 test circuits v+ dut v ms a b w v+ = v dd 1lsb = v+/256 01092-036 figure 37. potentiometer divider nonlinearity error (inl, dnl) dut v ms a b w no connect i w 01092-037 figure 38. resistor position nonlinearity error (rheostat operations; r-inl, r-dnl) a w b dut v ms1 v w i w =v dd /r nominal v ms2 r w =[v ms1 ?v ms2 ]/i w 01092-038 figure 39. wiper resistance v+ a b w ~ v a v ms v dd v+ = v dd 10% psrr (db) = 20log v ms v dd pss (%/%) = v ms % v dd % () 01092-039 figure 40. power supply sensitivity (pss, psrr) a v in 2.5v dc op279 5v v out ~ dut w offset gnd b 01092-040 figure 41. inverting programmable gain ~ a v in 2.5v op279 5 v v out dut w offset gnd b 01092-041 figure 42. noninverting programmable gain ~ b a v in 2.5v +15v v out dut w ?15v o ffset gnd op42 01092-042 figure 43. gain vs. frequency dut i sw b w v bias r sw = 0.1 v i sw code = 0.1v a=nc + ? 01092-043 h figure 44. incremental on resistance
ad8400/ad8402/ad8403 rev. e | page 20 of 32 theory of operation the ad8400/ad8402/ad8403 provide a single, dual, and quad channel, 256-position, digitally controlled variable resistor (vr) device. changing the programmed vr setting is accomplished by clocking in a 10-bit serial data-word into the sdi (serial data input) pin. the format of this data-word is two address bits, msb first, followed by eight data bits, also msb first. table 6 provides the serial register data-word format. the ad8400/ad8402/ad8403 have the following address assign- ments for the addr decoder, which determines the location of the vr latch receiving the serial register data in bit b7 to bit b0: vr# = a1 2 + a0 + 1 (1) the single-channel ad8400 requires a1 = a0 = 0. the dual- channel ad8402 requires a1 = 0. vr settings can be changed one at a time in random sequence. a serial clock running at 10 mhz makes it possible to load all four vrs under 4 s (10 4 100 ns) for ad8403. the exact timing requirements are shown in figure 3 , figure 4 , and figure 5 . the ad8400/ad8402/ad8403 do not have power-on midscale preset, so the wiper can be at any random position at power-up. however, the ad8402/ad8403 can be reset to midscale by asserting the rs pin, simplifying initial conditions at power-up. both parts have a power shutdown shdn pin that places the vr in a zero-power-consumption state where terminal ax is open-circuited and the wiper wx is connected to terminal bx, resulting in the consumption of only the leakage current in the vr. in shutdown mode, the vr latch settings are maintained so that upon returning to the operational mode, the vr settings return to the previous resistance values. the digital interface is still active in shutdown, except that sdo is deactivated. code changes in the registers can be made during shutdown that will produce new wiper positions when the device is taken out of shutdown. d7 d6 d5 d4 d3 d2 d1 d0 rdac latch and decoder ax wx bx r s =r nominal /256 r s shdn r s r s r s 01092-044 figure 45. ad8402/ad8403 equivalent vr (rdac) circuit programming the variable resistor rheostat operation the nominal resistance of the vr (rdac) between terminal a and terminal b is available with values of 1 k, 10 k, 50 k, and 100 k. the final digits of the part number determine the nominal resistance value; that is, 10 k = 10; 100 k = 100. the nominal resistance (r ab ) of the vr has 256 contact points accessible by the wiper terminal, and the resulting resistance can be measured either across the wiper and b terminals (r wb ) or across the wiper and a terminals (r wa ). the 8-bit data-word loaded into the rdac latch is decoded to select one of the 256 possible settings. the wipers first connection starts at the b terminal for data 00 h . this b terminal connection has a wiper contact resistance of 50 . the second connection (for the 10 k part) is the first tap point located at 89 = [r ab (nominal resistance) + r w = 39 + 50 ] for data 01 h . the third connection is the next tap point representing 78 + 50 = 128 for data 02 h . each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,011 . note that the wiper does not directly connect to the b terminal even for data 00 h . see figure 45 for a simplified diagram of the equivalent rdac circuit. the ad8400 contains one rdac, the ad8402 contains two independent rdacs, and the ad8403 contains four independent rdacs. the general transfer equation that determines the digitally programmed output resistance between wx and bx is () w ab wb rr d dr += (2) where d , in decimal, is the data loaded into the 8-bit rdac# latch, and r ab is the nominal end-to-end resistance. for example, when the a terminal is either open-circuited or tied to the wiper w, the following rdac latch codes result in the following r wb (for the 10 k version): table 10. d (dec) r wb ( ? ) output state 255 10,011 full scale 128 5,050 midscale ( rs = 0 condition) 1 89 1 lsb 0 50 zero-scale (wiper contact resistance) note that in the zero-scale condition, a finite wiper resistance of 50 is present. care should be taken to limit the current flow between w and b in this state to a maximum value of 5 ma to avoid degradation or possible destruction of the internal switch contact.
ad8400/ad8402/ad8403 rev. e | page 21 of 32 like a mechanical potentiometer, rdac is symmetrical. the resistance between the wiper w and terminal a also produces a digitally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be tied to the wiper or left floating. r wa starts at the maximum and decreases as the data loaded into the rdac latch increases. the general transfer equation for this r wa is () wab wa rr d dr + ? = 256 256 (3) where d is the data loaded into the 8-bit rdac# latch, and r ab is the nominal end-to-end resistance. for example, when the b terminal is either open-circuited or tied to the wiper w, the following rdac latch codes result in the following r wa (for the 10 k version): table 11. d (dec) r wa ( ? ) output state 255 89 full-scale 128 5,050 midscale ( rs = 0 condition) 1 10,011 1 lsb 0 10,050 zero-scale the typical distribution of rab from channel to channel matches within 1%. however, device-to-device matching is process lot dependent and has a 20% variation. the tem- perature coefficient, or the change in r ab with temperature, is 500 ppm/c. the wiper-to-end-terminal resistance temperature coefficient has the best performance over the 10% to 100% of adjustment range where the internal wiper contact switches do not con- tribute any significant temperature related errors. the graph in figure 18 shows the performance of r wb tempco vs. code. using the potentiometer with codes below 32 results in the larger temperature coefficients plotted. programming the potentiometer divider voltage output operation the digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. for example, connecting the a terminal to 5 v and the b termi- nal to ground produces an output voltage at the wiper starting at 0 v up to 1 lsb less than 5 v. each lsb is equal to the voltage applied across the a to b terminals divided by the 256-position resolution of the potentiometer divider. the general equation defining the output voltage with respect to ground for any given input voltage applied to the a to b terminals is bab w vv d v += 256 (4) operation of the digital potentiometer in the voltage divider mode results in more accurate operation over temperature. here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the temperature drift improves to 15 ppm/c. at the lower wiper position settings, the potentiometer divider temperature coefficient increases because the contribution of the cmos switch wiper resistance becomes an appreciable portion of the total resistance from the b terminal to the wiper w. see figure 17 for a plot of potentiometer tempco performance vs. code setting. digital interfacing the ad8400/ad8402/ad8403 contain a standard spi- compatible, 3-wire, serial input control interface. the three inputs are clock (clk), chip select ( cs ), and serial data input (sdi). the positive-edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. for the best result, use logic transitions faster than 1 v/s. standard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. the block diagrams in , , and show the internal digital circuitry in more detail. when figure 46 figure 47 figure 48 cs is taken active low, the clock loads data into the 10-bit serial register on each positive clock edge (see ). table 12 rdac latch no. 1 gnd a1 w1 b1 v dd ad8400 cs clk 8 d7 d0 en addr dec a1 a0 sdi di d0 d7 10-bit ser reg 0 1092-045 figure 46. ad8400 block diagram rdac latch no. 1 r agnd rs a1 w1 b1 v dd ad8402 cs clk d7 d0 rdac latch no. 2 r a4 w4 b4 d7 d0 en addr dec a1 a0 sdi di 10-bit ser reg d0 s hdn dgnd d7 8 01092-046 figure 47. ad8402 block diagram
ad8400/ad8402/ad8403 rev. e | page 22 of 32 rdac latch no. 1 r agnd rs a1 w1 b1 v dd ad8403 cs clk sdo d7 d0 rdac latch no. 4 r a4 w4 b4 d7 d0 en addr dec a1 a0 d7 sdi do di ser reg d0 shdn dgnd 8 01092-047 figure 48. ad8403 block diagram table 12. input logic control truth table 1 clk cs rs shdn register activity l l h h no sr effect; enables sdo pin p l h h shift one bit in from the sdi pin. the 10th previously entered bit is shifted out of the sdo pin. x p h h load sr data into rdac latch based on a1, a0 decode ( table 13 ). x h h h no operation x x l h sets all rdac latches to midscale, wiper centered, and sdo latch cleared x h p h latches all rdac latches to 80 h x h h l open-circuits all resistor a terminals, connects w to b, turns off sdo output transistor. 1 p = positive edge, x = dont care, sr = shift register the serial data output (sdo) pin, which exists only on the ad8403 and not on the ad8400 or ad8402, contains an open-drain, n-channel fet that requires a pull-up resistor to transfer data to the sdi pin of the next package. the pull-up resistor termination voltage may be larger than the v dd supply (but less than the max v dd of 8 v) of the ad8403 sdo output device. for example, the ad8403 could operate at v dd = 3.3 v, and the pull-up for interface to the next device could be set at 5 v. this allows for daisy-chaining several rdacs from a single proc- essor serial data line. the clock period needs to be increased when using a pull-up resistor to the sdi pin of the following device in the series. capacitive loading at the daisy-chain node sdo to sdi between devices must be accounted for in order to transfer data successfully. when daisy chain is used, cs should be kept low until all the bits of every package are clocked into their respective serial registers and the address and data bits are in the proper decoding location. if two ad8403 rdacs are daisy-chained, it requires 20 bits of address and data in the format shown in table 6 . during shutdown ( shdn = logic low), the sdo output pin is forced to the off (logic high) state to disable power dissipation in the pull-up resistor. see for equivalent sdo output circuit schematic. figure 50 the data setup and hold times in the specification table deter- mine the data valid time requirements. the last 10 bits of the data-word entered into the serial register are held when cs returns high. at the same time cs goes high it gates the address decoder, which enables one of the two (ad8402) or four (ad8403) positive edge-triggered rdac latches. see and . figure 49 table 13 table 13. address decode table a1 a0 latch decoded 0 0 rdac#1 0 1 rdac#2 1 0 rdac#3 ad8403 only 1 1 rdac#4 ad8403 only addr decode rdac 1 rdac 2 rdac 4 serial register a d8403 sdi clk cs 0 1092-048 figure 49. equivalent input control logic the target rdac latch is loaded with the last eight bits of the serial data-word completing one rdac update. in the case of ad8403, four separate 10-bit data-words must be clocked in to change all four vr settings. serial register sdi ck rs d shdn cs clk rs sdo 0 1092-049 q figure 50. detailed sdo output schematic of the ad8403 all digital pins are protected with a series input resistor and parallel zener esd structure shown in figure 51 . this structure applies to digital pins cs , sdi, sdo, rs , shdn , and clk. the digital input esd protection allows for mixed power supply applications where 5 v cmos logic can be used to drive an ad8400, ad8402, or ad8403 operating from a 3 v power supply. analog pin a, pin b, and pin w are protected with a 20 series resistor and parallel zener diode (see ). figure 52
ad8400/ad8402/ad8403 rev. e | page 23 of 32 1k digital pins logic 01092-050 figure 51. equivalent esd protection circuits 20 a ,b,w 01092-051 figure 52. equivalent esd prot ection circuit (analog pins) a c a c b w rd a c 10k b c w 120pf c a = 90.4pf (dw/256) + 30pf c b = 90.4pf [1 ? (dw/256)] + 30pf 01092-052 figure 53. rdac circuit simulation model for rdac = 10 k the ac characteristics of the rdac are dominated by the internal parasitic capacitances and the external capacitive loads. the ?3 db bandwidth of the ad8403an10 (10 k resistor) measures 600 khz at half scale as a potentiometer divider. figure 30 provides the large signal bode plot characteristics of the three available resistor versions 10 k, 50 k, and 100 k. the gain flatness vs. frequency graph of the 1 k version predicts filter applications performance (see figure 33 ). a parasitic simulation model has been developed and is shown in figure 53 . listing i provides a macro model net list for the 10 k rdac. listing i. macro model net list for rdac .param dw=255, rdac=10e3 * .subckt dpot (a,w,) * ca a 0 {dw/256*90.4e-12+30e-12} raw a w {(1-dw/256)*rdac+50} cw w 0 120e-12 rbw w b {dw/256*rdac+50} cb b 0 {(1-dw/256)*90.4e-12+30e-12} * .ends dpot the total harmonic distortion plus noise (thd + n), shown in figure 41 , is measured at 0.003% in an inverting op amp circuit using an offset ground and a rail-to-rail op279 amplifier. thermal noise is primarily johnson noise, typically 9 nv/hz for the 10 k version at f = 1 khz. for the 100 k device, thermal noise becomes 29 nv/hz. channel-to-channel crosstalk measures less than ?65 db at f = 100 khz. to achieve this isolation, the extra ground pins provided on the package to segregate the individual rdacs must be connected to circuit ground. agnd and dgnd pins should be at the same voltage potential. any unused potentiometers in a package should be connected to ground. power supply rejection is typically ?35 db at 10 khz. care is needed to minimize power supply ripple in high accuracy applications.
ad8400/ad8402/ad8403 rev. e | page 24 of 32 applications inverting gain (v/v) 256 128 0 0.1 1 10 96 64 32 160 192 224 digital code (decimal) 01092-053 the digital potentiometer (rdac) allows many of the applica- tions of a mechanical potentiometer to be replaced by a solid- state solution offering compact size and freedom from vibration, shock, and open contact problems encountered in hostile environments. a major advantage of the digital potentiometer is its programmability. any settings can be saved for later recall in system memory. the two major configurations of the rdac include the potentiometer divider (basic 3-terminal application) and the rheostat (2-terminal configuration) connections shown in figure 37 and figure 38 . certain boundary conditions must be satisfied for proper ad8400/ad8402/ad8403 operation. first, all analog signals must remain within the gnd to v dd range used to operate the single-supply ad8400/ad8402/ad8403. for standard potentiometer divider applications, the wiper output can be used directly. for low resistance loads, buffer the wiper with a suitable rail-to-rail op amp such as the op291 or the op279. second, for ac signals and bipolar dc adjustment applications, a virtual ground is generally needed. whichever method is used to create the virtual ground, the result must provide the necessary sink and source current for all connected loads, including adequate bypass capacitance. figure 41 shows one channel of the ad8402 connected in an inverting programmable gain amplifier circuit. the virtual ground is set at 2.5 v, which allows the circuit output to span a 2.5 v range with respect to virtual ground. the rail-to-rail amplifier capability is necessary for the widest output swing. as the wiper is adjusted from its midscale reset position (80 h ) toward the a terminal (code ff h ), the voltage gain of the circuit is increased in successively larger increments. alternatively, as the wiper is adjusted toward the b terminal (code 00 h ), the signal becomes attenuated. the plot in figure 54 shows the wiper settings for a 100:1 range of voltage gain (v/v). note the 10 db of pseudologarithmic gain around 0 db (1 v/v). this circuit is mainly useful for gain adjustments in the range of 0.14 v/v to 4 v/v; beyond this range the step sizes become very large, and the resistance of the driving circuit can become a significant term in the gain equation. figure 54. inverting programmable gain plot active filter the state variable active filter is one of the standard circuits used to generate a low-pass, high-pass, or band-pass filter. the digital potentiometer allows full programmability of the frequency, gain, and q of the filter outputs. figure 55 shows the filter circuit using a 2.5 v virtual ground, which allows a 2.5 v p input and output swing. rdac2 and rdac3 set the lp, hp, and bp cutoff and center frequencies, respectively. these variable resistors should be programmed with the same data (as with ganged potentiometers) to maintain the best circuit q. figure 56 shows the measured filter response at the band-pass output as a function of the rdac2 and rdac3 settings that produce a range of center frequencies from 2 khz to 20 khz. the filter gain response at the band-pass output is shown in figure 57 . at a center frequency of 2 khz, the gain is adjusted over a ?20 db to +20 db range determined by rdac1. circuit q is adjusted by rdac4. for more detailed reading on the state variable active filter, see analog devices application note an-318. a1 rdac1 v in b a2 a3 a4 rdac4 b 10k 10k op279 2 rdac2 rdac3 b b 0.01 f 0.01 f band- pass high- pass low- pass 0 1092-054 figure 55. programmable state variable active filter
ad8400/ad8402/ad8403 rev. e | page 25 of 32 frequency (hz) 40 20 ?80 20 100k 100 1k 10k 0 ?20 ?40 ?60 200k amplitude (db) ?0.16 20.0000 k 01092-055 figure 56. programmed center frequency band-pass response frequency (hz) 40 20 ?80 20 100k 100 1k 10k 0 ?20 ?40 ?60 200k amplitude (db) ?19.01 2.00000 k 01092-056 figure 57. programmed amplitude band-pass response
ad8400/ad8402/ad8403 rev. e | page 26 of 32 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 58. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) 14 1 7 8 0.100 (2.54) bsc 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 59. 14-lead plastic dual-in-line package [pdip] narrow body (n-14) dimensions shown in inches and (millimeters)
ad8400/ad8402/ad8403 rev. e | page 27 of 32 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ab 060606-a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 45 figure 60. 14-lead standard small outline package [soic_n] narrow body (r-14) dimensions shown in millimeters and (inches) compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 61. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters
ad8400/ad8402/ad8403 rev. e | page 28 of 32 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001 071006-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 24 1 12 13 0.100 (2.54) bsc 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 62. 24-lead plastic dual-in-line package [pdip] narrow body (n-24-1) dimensions shown in inches and (millimeters) compliant to jedec standards ms-013-ad controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 24 13 12 1 1.27 (0.0500) bsc 06-07-2006-a figure 63. 24-lead standard small outline package [soic_w] wide body (rw-24) dimensions shown in millimeters and (inches)
ad8400/ad8402/ad8403 rev. e | page 29 of 32 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 64. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters
ad8400/ad8402/ad8403 rev. e | page 30 of 32 ordering guide model 1, 2, 3 number of channels end-to-end r ab (k) temperature range (c) package description package option ordering quantity branding information ad8400ar10 1 10 ?40 to +125 8-lead soic_n r-8 98 ad8400a10 ad8400ar10-reel 1 10 ?40 to +125 8- lead soic_n r-8 2,500 ad8400a10 ad8400arz10 1 10 ?40 to +125 8-lead soic_n r-8 98 ad8400a10 ad8400arz10-reel 1 10 ?40 to +125 8-lead soic_n r-8 2,500 ad8400a10 ad8400ar50 1 50 ?40 to +125 8-lead soic_n r-8 98 ad8400a50 ad8400ar50-reel 1 50 ?40 to +125 8- lead soic_n r-8 2,500 ad8400a50 ad8400arz50 1 50 ?40 to +125 8-lead soic_n r-8 98 ad8400a50 ad8400arz50-reel 1 50 ?40 to +125 8-lead soic_n r-8 2,500 ad8400a50 ad8400ar100 1 100 ?40 to +125 8-lead soic_n r-8 98 ad8400ac ad8400ar100-reel 1 100 ?40 to +125 8-lead soic_n r-8 2,500 ad8400ac ad8400arz100 1 100 ?40 to +125 8-lead soic_n r-8 98 ad8400ac ad8400arz100-reel 1 100 ?40 to +125 8-lead soic_n r-8 2,500 ad8400ac ad8400ar1 1 1 ?40 to +125 8-lead soic_n r-8 98 ad8400a1 ad8400ar1-reel 1 1 ?40 to +125 8- lead soic_n r-8 2,500 ad8400a1 ad8400arz1 1 1 ?40 to +125 8-lead soic_n r-8 98 ad8400a1 ad8400arz1-reel 1 1 ?40 to +125 8-lead soic_n r-8 2,500 ad8400a1 ad8402an10 2 10 ?40 to +125 14-lead pdip n-14 25 ad8402a10 ad8402anz10 2 10 ?40 to +125 14-lead pdip n-14 25 ad8402a10 ad8402ar10 2 10 ?40 to +125 14-lead soic_n r-14 56 ad8402a10 ad8402ar10-reel 2 10 ?40 to +125 14- lead soic_n r-14 2,500 ad8402a10 ad8402aru10 2 10 ?40 to +125 14-lead tssop ru-14 96 8402a10 ad8402aru10-reel 2 10 ?40 to +125 14-lead tssop ru-14 2,500 8402a10 ad8402aruz10 2 10 ?40 to +125 14-lead tssop ru-14 96 8402a10 ad8402aruz10-reel 2 10 ?40 to +125 14-lead tssop ru-14 2,500 8402a10 ad8402arz10 2 10 ?40 to +125 14-lead soic_n r-14 96 ad8402a10 ad8402arz10-reel 2 10 ?40 to +125 14-lead soic_n r-14 2,500 ad8402a10 ad8402ar50 2 50 ?40 to +125 14-lead soic_n r-14 56 ad8402a50 ad8402ar50-reel 2 50 ?40 to +125 14- lead soic_n r-14 2,500 ad8402a50 ad8402aru50 2 50 ?40 to +125 14-lead tssop ru-14 96 8402a50 ad8402aru50-reel 2 50 ?40 to +125 14-lead tssop ru-14 2,500 8402a50 ad8402aruz50 2 50 ?40 to +125 14-lead tssop ru-14 96 8402a50 ad8402aruz50-reel 2 50 ?40 to +125 14-lead tssop ru-14 2,500 8402a50 ad8402arz50 2 50 ?40 to +125 14-lead soic_n r-14 96 ad8402a50 ad8402arz50-reel 2 50 ?40 to +125 14-lead soic_n r-14 2,500 ad8402a50 ad8402ar100 2 100 ?40 to +125 14-lead soic_n r-14 56 ad8402ac ad8402ar100-reel 2 100 ?40 to +125 14-lead soic_n r-14 2,500 ad8402ac ad8402aru100 2 100 ?40 to +125 14-lead tssop ru-14 96 8402a-c ad8402aru100-reel 2 100 ?40 to +125 14-lead tssop ru-14 2,500 8402a-c ad8402aruz100 2 100 ?40 to +125 14-lead tssop ru-14 96 8402a-c ad8402aruz100-reel 2 100 ?40 to +125 14-lead tssop ru-14 2,500 8402a-c ad8402arz100 2 100 ?40 to +125 14-lead soic_n r-14 96 ad8402ac ad8402arz100-reel 2 100 ?40 to +125 14-lead soic_n r-14 2,500 ad8402ac ad8402ar1 2 1 ?40 to +125 14-lead soic_n r-14 56 ad8402a1 ad8402ar1-reel 2 1 ?40 to +125 14- lead soic_n r-14 2,500 ad8402a1 ad8402aru1 2 1 ?40 to +125 14-lead tssop ru-14 96 8402a1 ad8402aruz1 2 1 ?40 to +125 14-lead tssop ru-14 96 ad8402a1 ad8402aruz1-reel 2 1 ?40 to +125 14-lead tssop ru-14 2,500 ad8402a1 ad8402arz1 2 1 ?40 to +125 14-lead soic_n r-14 56 ad8402a1 ad8402arz1-reel 2 1 ?40 to +125 14-lead soic_n r-14 2,500 ad8402a1
ad8400/ad8402/ad8403 rev. e | page 31 of 32 model 1, 2, 3 number of channels end-to-end r ab (k) temperature range (c) package description package option ordering quantity branding information ad8403an10 4 10 ?40 to +125 24-lead pdip n-24-1 15 ad8403a10 ad8403ar10 4 10 ?40 to +125 24-lead soic_w rw-24 31 ad8403a10 ad8403ar10-reel 4 10 ?40 to +125 24-lead soic_w rw-24 1,000 ad8403a10 ad8403aru10 4 10 ?40 to +125 24-lead tssop ru-24 63 8403a10 ad8403aru10-reel 4 10 ?40 to +125 24-lead tssop ru-24 2,500 8403a10 ad8403aruz10 4 10 ?40 to +125 24-lead tssop ru-24 63 8403a10 ad8403aruz10-reel 4 10 ?40 to +125 24-lead tssop ru-24 2,500 8403a10 ad8403arz10 4 10 ?40 to +125 24-lead soic_w rw-24 63 ad8403a10 ad8403arz10-reel 4 10 ?40 to +125 24-lead soic_w rw-24 2,500 ad8403a10 ad8403an50 4 50 ?40 to +125 24-lead pdip n-24-1 15 ad8403a50 ad8403ar50 4 50 ?40 to +125 24-lead soic_w rw-24 31 ad8403a50 ad8403ar50-reel 4 50 ?40 to +125 24-lead soic_w rw-24 1,000 ad8403a50 ad8403aru50 4 50 ?40 to +125 24-lead tssop ru-24 63 8403a50 ad8403aruz50 4 50 ?40 to +125 24-lead tssop ru-24 2,500 8403a50 ad8403aruz50-reel 4 50 ?40 to +125 24-lead tssop ru-24 2,500 8403a50 ad8403arz50 4 50 ?40 to +125 24-lead soic_w rw-24 63 ad8403a50 ad8403arz50-reel 4 50 ?40 to +125 24-lead soic_w rw-24 2,500 ad8403a50 ad8403ar100 4 100 ?40 to +125 24-lead soic_w rw-24 31 ad8403a100 ad8403ar100-reel 4 100 ?40 to +125 24-lead soic_w rw-24 1,000 ad8403a100 ad8403aru100 4 100 ?40 to +125 24-lead tssop ru-24 63 8403a100 ad8403aru100-reel 4 100 ?40 to +125 24-lead tssop ru-24 2,500 8403a100 ad8403aruz100 4 100 ?40 to +125 24-lead tssop ru-24 63 8403a100 ad8403aruz100-reel 4 100 ?40 to +125 24-lead tssop ru-24 2,500 8403a100 AD8403ARZ100 4 100 ?40 to +125 24-lead soic_w rw-24 63 ad8403a100 AD8403ARZ100-reel 4 100 ?40 to +125 24-lead soic_w rw-24 2,500 ad8403a100 ad8403ar1 4 1 ?40 to +125 24-lead soic_w rw-24 31 ad8403a1 ad8403ar1-reel 4 1 ?40 to +125 24-lead soic_w rw-24 1,000 ad8403a1 ad8403aru1 4 1 ?40 to +125 24-lead tssop ru-24 63 8403a1 ad8403aru1-reel 4 1 ?40 to +125 24-lead tssop ru-24 2,500 8403a1 ad8403aruz1 4 1 ?40 to +125 24-lead tssop ru-24 63 8403a1 ad8403aruz1-reel 4 1 ?40 to +125 24-lead tssop ru-24 2,500 8403a1 ad8403arz1 4 1 ?40 to +125 24-lead soic_w rw-24 63 ad8403a1 ad8403arz1-reel 4 1 ?40 to +125 24-lead soic_w rw-24 2,500 ad8403a1 ad8403warz50-reel 4 50 ?40 to +125 24-lead soic_w rw-24 2,500 eval-ad8403sdz evaluation board 1 non-lead-free parts have date codes in the format of either yww or yyww, and lead-free parts have date codes in the format of #yww, where y/yy is the year of production and ww is the work week. for example, a non-lead-free part manufactured in the 30 th work week of 2005 has the date code of either 530 or 0530, while a lead-free part has the date code of #530. 2 z = rohs compliant part. 3 w = qualified for auto motive applications. automotive products the ad8403w models are available with controlled manufacturing to support the quality and reliability requirements of automotiv e applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models.
ad8400/ad8402/ad8403 rev. e | page 32 of 32 notes ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d01092-0-7/10(e)

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